Clocking signals for the CCD are generated by a microcontroller-based clock generator and clock drivers, which are housed in the digital electronics box.
Table 9: Clock Generator Waveforms, Amp 3
The clock generator architecture and design are based on our laboratory and rocket cameras, but the CUBIC clock generator has been modified to use different components that provide radiation hardness and meet the low power requirements of CUBIC .
The microcontroller for the CUBIC clock generator is a Dallas Semiconductors DS80C320-MNG. Instructions are stored in a 32K 8 bit EEPROM (Seeq DM28C256) which can hold up to 64 different clock waveform codes (selectable by serial command). The clock waveforms are listed in Table 9 and Table 10.
Table 10: Clock Generator Waveforms, Amp 4
The clocks are driven using bilevel driver modules controlled by TTL bit patterns stored in ROM located in the same 32K address space as the microcontroller program code. Bit patterns are stored in three identical 32K 8 EEPROMs to accommodate up to 24 digital waveforms. Bit assignments are given in Table 11. Clock bits that are inverted by the driving circuitry before reaching the CCD or circuitry that they control are indicated in the comments. (Inverted clock bits must be set in software to the opposite level of the intended result. For example, the clock phase control bits must be set to 0 to obtain a high clock level at the CCD.)
Table 11: CCD Clock Driver Bit Assignments
As the microcontroller steps through the waveform code, the bit patterns at the corresponding addresses are sent to the Clock Driver Board where they are combined with analog voltages selected by DACs to produce the analog clocking signals needed by the CCDs. The signals from the single clock generator are multiplexed on the clock driver board, and each CCD has independent clock drivers and clock signal wires.
Samples of the clock waveforms for readout mode 5 are shown in Figures 20 and 21.
These show the clock logic levels seen at the CCD for the CCD clocks, or seen on the Signal Chain Board for the Signal Chain control signals (EPSC, SAMPLE/HOLD, CLAMP, and SC). Both figures are for the normal readout sequence for Amp 3 (waveform #5). Figure 20 shows the overall waveform sequence (not to scale). The waveform begins by flushing the frame-store area to clear out any charge deposited by cosmic rays during integration. It then transfers the signal packets from the Image Area to the Frame Store Area and performs a flush of the serial register. It then begins the readout sequence, in which each row of pixels is transferred into the serial register and then readout through Amp 3.
The readout sequence in the serial register is shown in Figure 21, which is to scale. This timing is the most
critical for achieving low noise performance. The first event in a single pixel readout is that charge is dumped from the phase 1 gate to the phase 2 gate. Next, the charge is transferred onto the phase 3 gate and then shared between phases 3 and 1. After a settling period to allow clock feedthroughs to die away, the SC pulse is sent to the ADC to initiate digitization of the previous pixel's video signal. Following the A/D conversion, the current pixel's video signal is dumped onto the output node and the SAMPLE period begins. The clamp is released 400 ns after the video dump to reduce noise caused by the phase 3 clock feedthrough. After a s sample time, the video signal is held for digitization. The postamp output is clamped again after a small delay and the output node is reset. The cycle then repeats. The baseline correction circuit samples the output video signal during the final s of the pixel read cycle in the extended pixels.
Frame timing is controlled by a hardware timer interrupt on the ICP (Next Frame Interrupt). The time interval () is set by serial command SC11 to of the desired CCD exposure time (which is typically 40 seconds). At the end of each time interval, a Next Frame Interrupt is generated and is processed by the ICP, which selects the desired waveform and initiates the clock generator. Since the ICP alternates between CCDs, each CCD is read out every other Next Frame Interrupt. The CCD frame timing is shown in Figure 22.
The readout cycle consists of a transfer of the data from the image area to the frame-store area, followed by readout and digitization of the data in the framestore area. After a short interval to collect housekeeping data and process any serial commands that have arrived, the next frame is read out from the other CCD.